IPC in the 10’s via Resource Flow Computing with Levo

High ILP (Instruction Level Parallelism) exists in typical integer codes. Our goal is to create a machine called Levo that will realize this potential ILP in the face of real hardware limitations. Levo is modeled and evaluated at three different levels of abstraction. FastLevo models the potential of Levo via high-level trace-driven simulation embodying key hardware constraints. LevoSim is a detailed cycle-accurate execution-driven simulator; it gives us precise performance data on the Levo architecture. Lastly, HDLevo is a synthesizable VHDL model of the key elements of Levo; it gives us detailed Levo hardware cost estimates. Levo has many novel architectural features, including the use of time tags with instructions to implicitly enforce data and control dependencies. Levo provides a registerless data path, in that there is no central register file or bottleneck. A resource-flow model of computation is used in which instructions execute whenever resources are available, regardless of true data or control dependencies. Levo obtains this high IPC with scalability in our hardware implementation. FastLevo shows IPC’s in the 10’s over a wide range of Levo configurations on a subset of the SPECint2000 benchmarks allowing for relaxed memory and control dependencies, though real machine hardware and data dependencies. With HDLevo we obtain a hardware cost for the Levo core (no PE’s, memory or I-fetch) of less than 59 million transistors.